1. Field of the Invention
The present invention relates to a semiconductor device.
2. Description of Related Art
Techniques have been proposed for forming uneven surfaces such as trenches in the channel region of a substrate, to increase the effective channel width of a transistor without an increase in size.
For example, Japanese Patent Laid-Open No. H11-103058, corresponding to U.S. Pat. No. 6,452,231, and Japanese Patent Laid-Open No. S51-147269 describe a semiconductor device including a trench transistor structure in which trenches are formed on the substrate surface. Japanese Patent Laid-Open No. 2007-5568, corresponding to U.S. Pat. No. 7,391,068, describes a semiconductor device in which a plurality of projecting silicon regions are formed in the width direction of a channel region formed between a source region and a drain region which are formed on a semiconductor substrate. A gate insulating film and a gate electrode are formed facing the channel region on the silicon projections. A reduction in the pitch of the gates reduces the width of the projections and achieves full depletion of a depletion layer in the projections during the operation of transistors, thus mitigating the short channel effect and improving the subthreshold slope (Japanese Patent Laid-Open No. 2005-085960, corresponding to U.S. Pat. No. 6,919,601). It is also possible to use, as an advantage, such a decrease in the substrate bias dependence of threshold voltage due to such full depletion in an appropriate circuit configuration. Japanese Patent Laid-Open No. 2008-53468 describes a technique which involves performing oblique ion implantation on a substrate in which trenches are formed and performing thermal diffusion thereafter.
However, the present inventors discovered that trench transistor structures such as those described in U.S. Pat. No. 6,452,231, Japanese Patent Laid-Open No. S51-147269, U.S. Pat. No. 7,391,068 and U.S. Pat. No. 6,919,601 have a problem in that, despite applying a constant voltage to a gate electrode, the variation in the shape of the gate electrode creates electric field concentration at the top and bottom regions of the trenches, such that the electric field becomes high in these regions. For this reason, a localized decrease in threshold voltage occurs. Regions where the threshold voltage has decreased in this manner act like parasitic transistors and phenomena such as hump and kink occur; that is, a drain current flows at a lower gate voltage. The subthreshold characteristics of such transistors are thereby compromised.